GSS EU Science Funding Gateway

The overall goal is to develop RISC-V to become a widespread industry standard alternative to today’s proprietary Instruction Set Architectures (ISA). For this, RISC-V needs a powerful ecosystem comprising technology, business models and pioneering usecase applications.

Proposals for this call will develop RISC-V compliant IP blocks. Certain IP blocks may be proprietary solutions; however, a large share of developed building blocks provided with a permissive open-source licence is preferred. All developed blocks must come with publicly available documentation, benchmarks, verification suites, and validated reference designs (including firmware/drivers, if required). For this call, the RISC-V architectural aspect of the proposed IP building blocks should be clearly identifiable. Furthermore, each IP block should be able to demonstrate the optimisation goals it was designed for (low power, high security, processing acceleration, etc.) in realistic application contexts and appropriate use cases.

There is a list of building blocks of which some must be developed in the proposed project (see p. 28 of the work programme) In addition, the selected building blocks must support the common European roadmap and the ecosystem for RISC-V. In addition to the list of RISC-V blocks, the following technologies are considered as examples of useful complements to the base blocks, and are considered in scope for this call if developed in open-source form, again with documentation, verification and validation suites:

• Holistic architectural approaches for HW/SW co-design of computing systems (compilers, design tools, architectural extensions or microarchitectures targeting various semiconductor technologies) under open-source licenses.
• Chiplet, interposer and especially high-bandwidth, low-latency, low-energy die-to-die communication technologies.
• Template PCB designs for PCIe-attached accelerators, similar to existing FPGA evaluation/prototyping boards, but allowing the easy integration of a user-provided ASIC instead of an FPGA,
• Communication peripheral interfaces, specifically Ethernet (at least 1G) and USB (at least 2.0).